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M48Z129Y M48Z129V
5.0 V or 3.3 V, 1 Mbit (128 Kb x 8) ZEROPOWER(R) SRAM
Features

Integrated, ultra low power SRAM, power-fail control circuit, and battery Conventional SRAM operation; unlimited WRITE cycles 10 years of data retention in the absence of power Microprocessor power-on reset (reset valid even during battery backup mode) Battery low pin - provides warning of battery end-of-life Automatic power-fail chip deselect and WRITE protection WRITE protect voltages (VPFD = power-fail deselect voltage): - M48Z129Y: VCC = 4.5 to 5.5 V 4.2 V VPFD 4.5 V (contact the ST sales office for availability) - M48Z129V: VCC = 3.0 to 3.6 V 2.7 V VPFD 3.0 V Self-contained battery in the CAPHATTM DIP package Pin and function compatible with JEDEC standard 128 K x 8 SRAMs RoHS compliant - Lead-free second level interconnect
32 1
PMDIP32 module (PM)

June 2010
Doc ID 5716 Rev 7
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www.st.com 1
Contents
M48Z129Y, M48Z129V
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 4 5 6 7 8
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 - 32-pin plastic DIP, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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List of figures
M48Z129Y, M48Z129V
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address controlled, READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chip enable or output enable controlled, READ mode AC waveforms. . . . . . . . . . . . . . . . . 8 WRITE enable controlled, WRITE mode AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip enable controlled, WRITE mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 PMDIP32 - 32-pin plastic module DIP, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Description
1
Description
The M48Z129Y/V ZEROPOWER(R) SRAM is a 1,048,576 bit non-volatile static RAM organized as 131,072 words by 8 bits. The device combines an internal lithium battery, a CMOS SRAM and a control circuit in a plastic 32-pin DIP module. The M48Z129Y/V directly replaces industry standard 128 K x 8 SRAM. It also provides the non-volatility of FLASH without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. Figure 1. Logic diagram
VCC
17 A0-A16 W E G M48Z129Y M48Z129V
8 DQ0-DQ7 RST BL
VSS
AI02309
Table 1.
Signal names
A0-A16 Address inputs Data inputs / outputs Chip enable Output enable WRITE enable Reset output (open drain) Battery low output (open drain) Supply voltage Ground
DQ0-DQ7 E G W RST BL VCC VSS
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Description Figure 2. DIP connections
RST A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 32 2 31 30 3 29 4 28 5 27 6 26 7 8 M48Z129Y 25 9 M48Z129V 24 23 10 22 11 21 12 20 13 19 14 18 15 17 16 VCC A15 BL W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
M48Z129Y, M48Z129V
AI02310
Figure 3.
Block diagram
VCC
A0-A16
POWER E VOLTAGE SENSE AND SWITCHING CIRCUITRY
131,072 x 8 SRAM ARRAY
DQ0-DQ7
E
W G
INTERNAL BATTERY
RST
BL
VSS
AI03608
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Operation modes
2
Operation modes
The M48Z129Y/V also has its own power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing data security in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery, maintaining data until valid power is restored. Table 2.
Mode Deselect WRITE READ READ Deselect Deselect
1.
Operating modes
VCC 4.5 to 5.5 V or 3.0 to 3.6 V VSO to VPFD (min)(1) E VIH VIL VIL VIL X X VSO(1) G X X VIL VIH X X W X VIL VIH VIH X X DQ0-DQ7 High Z DIN DOUT High Z High Z High Z Power Standby Active Active Active CMOS standby Battery backup mode
See Table 10 for details.
Note:
X = VIH or VIL; VSO = battery backup switchover voltage
2.1
READ mode
The M48Z129Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip enable) is low. The unique address specified by the 17 address inputs defines which one of the 131,072 bytes of data is to be accessed. Valid data will be available at the data I/O pins within tAVQV (address access time) after the last address input signal is stable, providing the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the chip enable access times (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E and G remain active, output data will remain valid for tAXQX (output data hold time) but will go indeterminate until the next address access. Figure 4. Address controlled, READ mode AC waveforms
tAVAV A0-A16 tAVQV tAXQX DQ0-DQ7 DATA VALID DATA VALID AI02324 VALID
Note:
Chip enable (E) and output enable (G) = low, WRITE enable (W) = high
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Operation modes Figure 5.
M48Z129Y, M48Z129V Chip enable or output enable controlled, READ mode AC waveforms
tAVAV A0-A16 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 DATA OUT AI01197 tGHQZ VALID tAXQX tEHQZ
Table 3.
READ mode AC characteristics
M48Z129Y M48Z129V -85 Max Min 85 70 70 35 5 3 30 20 5 5 5 5 40 25 85 85 45 Max ns ns ns ns ns ns ns ns ns Unit
Symbol
Parameter(1) Min
-70
tAVAV tAVQV tELQV tGLQV tELQX
(2)
READ cycle time Address valid to output valid Chip enable low to output valid Output enable low to output valid Chip enable low to output transition Output enable low to output transition Chip enable high to output Hi-Z Output enable high to output Hi-Z Address transition to output transition
70
tGLQX(2) tEHQZ(2) tGHQZ(2) tAXQX
1. 2.
Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). CL = 5pF (see Figure 9).
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Operation modes
2.2
WRITE mode
The M48Z129Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable) are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. Figure 6. WRITE enable controlled, WRITE mode AC waveform
tAVAV A0-A16 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH AI02382 tWHQX tWHAX
Figure 7.
Chip enable controlled, WRITE mode AC waveforms
tAVAV
A0-A16
VALID tAVEH tAVEL tELEH tEHAX
E tWLWH tAVWL W
tDVEH DQ0-DQ7 DATA INPUT
tEHDX
AI03611
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Operation modes Table 4. WRITE mode AC characteristics
M48Z129Y Symbol Parameter(1) Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ(2)(3) tAVWH tAVEH tWHQX(2)(3)
1. 2. 3.
M48Z129Y, M48Z129V
M48Z129V -85 Unit Max ns ns ns ns ns ns ns ns ns ns ns 30 75 75 5 ns ns ns ns
-70 Max Min 85 0 0 65 75 5 15 35 35 0 15 25 65 65 5
WRITE cycle time Address valid to WRITE enable low Address valid to chip enable low WRITE enable pulse width Chip enable low to chip enable high WRITE enable high to address transition Chip enable high to address transition Input valid to WRITE enable high Input valid to chip enable high WRITE enable high to input transition Chip enable high to input transition WRITE enable low to output Hi-Z Address valid to WRITE enable high Address valid to chip enable high WRITE enable high to output transition
70 0 0 55 55 5 15 30 30 0 10
Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). CL = 5 pF (see Figure 9). If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid VCC applied, the M48Z129Y/V operates as a conventional BYTEWIDETM static RAM. Should the supply voltage decay, the RAM will automatically deselect, write protecting itself when VCC falls between VPFD (max), VPFD (min) window. All outputs become high impedance and all inputs are treated as "Don't care".
Note:
A power failure during a WRITE cycle may corrupt data at the current addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48Z129Y/V may respond to transient noise spikes on VCC that cross into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery, preserving data. The internal energy source will maintain data in the M48Z129Y/V for an accumulated period of at least 10 years at room temperature. As system power rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC after VCC reaches VPFD(max). For more information on battery storage life refer to the application note AN1012.
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Operation modes
2.4
VCC noise and negative going transients
ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 F (as shown in Figure 8) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 8. Supply voltage protection
VCC VCC
0.1F
DEVICE
VSS AI02169
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Maximum ratings
M48Z129Y, M48Z129V
3
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5.
Symbol TA TSTG TSLD(1) VIO VCC IO PD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature (VCC off, oscillator off) Lead solder temperature for 10 seconds Input or output voltages Supply voltage Output current Power dissipation Value 0 to 70 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1 Unit C C C V V mA W
1. Soldering temperature of the IC leads is to not exceed 260 C for 10 seconds. In order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 C. Furthermore, the devices shall not be exposed to IR reflow.
Caution:
Negative undershoots below -0.3 V are not allowed on any pin while in the battery backup mode.
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DC and AC parameters
4
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 6. Operating and AC measurement conditions
Parameter Supply voltage (VCC) Ambient operating temperature (TA) Load capacitance (CL) Input rise and fall times Input pulse voltages Input and output timing ref. voltages M48Z129Y 4.5 to 5.5 0 to 70 100 5 0 to 3 1.5 M48Z129V 3.0 to 3.6 0 to 70 50 5 0 to 3 1.5 Unit V C pF ns V V
Note:
Output Hi-Z is defined as the point where data is no longer driven. Figure 9. AC testing load circuit
DEVICE UNDER TEST 650
CL = 100pF or 50pF(1)
1.75V
CL includes JIG capacitance
AI03630
1. 50 pF for M48Z129V (3.3 V).
Table 7.
Symbol CIN CIO
(3)
Capacitance
Parameter(1)(2) Input capacitance Input / output capacitance Min Max 10 10 Unit pF pF
1. Effective capacitance measured with power supply at 5 V; sampled only, not 100% tested. 2. At 25 C, f = 1 MHz. 3. Outputs deselected.
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DC and AC parameters Table 8. DC characteristics
M48Z129Y Sym Parameter Test condition(1) Min ILI ILO(2) ICC ICC1 ICC2 VIL VIH VOL VOH Input leakage current Output leakage current Supply current Supply current (standby) TTL Supply current (standby) CMOS Input low voltage Input high voltage Output low voltage Output high voltage IOL = 2.1 mA IOH = -1 mA 2.4 0 V VIN VCC 0 V VOUT VCC Outputs open E = VIH E = VCC - 0.2 V -0.3 2.2 -70 Max 1 1 95 7 4 0.8 VCC + 0.3 0.4
M48Z129Y, M48Z129V
M48Z129V -85 Min Max 1 1 50 4 3 -0.3 2.2 0.6 VCC + 0.3 0.4 2.2 A A mA mA mA V V V V Unit
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. Outputs deselected.
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M48Z129Y, M48Z129V Figure 10. Power down/up mode AC waveforms
VCC VPFD (max) VPFD (min) VSO tF tFB tWPT E
RECOGNIZED
DC and AC parameters
tDR tRB
tR tREC
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
RST AI03610
Table 9.
Symbol tF(2) tFB(3) tR tRB tWPT tREC
Power down/up AC characteristics
Parameter(1) VPFD (max) to VPFD (min) VCC fall time M48Z129Y VPFD (min) to VSS VCC fall time VPFD (min) to VPFD (max) VCC rise time VSS to VPFD (min) VCC rise time M48Z129Y Write protect time M48Z129V VPFD (max) to RST high 40 40 250 200 ms M48Z129V Min 300 10 s 150 10 1 40 150 s s s Max Unit s
1. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 10.
Symbol VPFD
Power down/up trip points DC characteristics
Parameter(1)(2) M48Z129Y Power-fail deselect voltage M48Z129V M48Z129Y Battery backup switchover voltage M48Z129V Expected data retention time 10 2.45 V Years 2.7 2.9 3.0 3.0 V V Min 4.2 Typ 4.35 Max 4.5 Unit V
VSO tDR(3)
1. All voltages referenced to VSS. 2. Valid for ambient operating temperature: TA = 0 to 70 C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 3. At 25 C, VCC = 0 V.
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Package mechanical data
M48Z129Y, M48Z129V
5
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 11. PMDIP32 - 32-pin plastic module DIP, package outline
A
A1 S B e3 D e1
L eA
C
N
E
1
PMDIP
Note:
Drawing is not to scale. Table 11.
Symb Typ A A1 B C D E e1 e3 eA L S N 38.1 14.99 3.05 1.91 32 16.00 3.81 2.79 Min 9.27 0.38 0.43 0.20 42.42 18.03 2.29 Max 9.52 - 0.59 0.33 43.18 18.80 2.79 1.5 0.590 0.120 0.075 32 0.630 0.150 0.110 Typ Min 0.365 0.015 0.017 0.008 1.670 0.710 0.090 Max 0.375 - 0.023 0.013 1.700 0.740 0.110
PMDIP32 - 32-pin plastic DIP, package mechanical data
mm inches
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Part numbering
6
Part numbering
Table 12.
Example:
Ordering information scheme
M48Z 129Y -70 PM 1
Device Type M48Z
Supply voltage and write protect voltage 129Y(1) = VCC = 4.5 to 5.5 V; 4.2 V VPFD 4.5 V 129V = VCC = 3.0 to 3.6 V; 2.7 V VPFD 3.0 V
Speed -70 = 70 ns (M48Z129Y) -85 = 85 ns (M48Z129V)
Package PM = PMDIP32
Temperature range 1 = 0 to 70 C
Shipping method blank = ECOPACK(R) package, tubes
1. Contact local ST sales office.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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Environmental information
M48Z129Y, M48Z129V
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. Please refer to the following web site address for additional information regarding compliance statements and waste recycling. Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
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Revision history
8
Revision history
Table 13.
Date Dec-1999 30-Mar-2000 20-Jun-2000 14-Sep-2001 29-May-2002 02-Apr-2003 18-Feb-2005 22-Apr-2010 23-Jun-2010
Document revision history
Revision 1.0 2 2.1 3 3.1 4 5 6 7 First issue From preliminary data to datasheet tGLQX changed for M48Z129Y (Table 3) Reformatted; temperature information added to tables (Table 7, 8, 3, 4, 9, 10) Add countries to disclaimer v2.2 template applied; test condition updated (Table 10) Reformatted; IR reflow update (Table 5) Updated Table 11, 12, footnote 1 of Table 5; added Ecopack(R) text to Section 5; reformatted document. Updated Features, Table 11; added Section 7: Environmental information; minor textual changes. Changes
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M48Z129Y, M48Z129V
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